Low jitter design for quarter-rate CDR of 100Gb/s PAM4 optical receiver

In the ultra-high speed four-level pulse amplitude modulation (PAM4) optical receiver, data phase jitter is deteriorated by inter-symbol interference (ISI), level transitions and sampling clock. This paper analyzed in detail causes of jitter, then proposed a novel PAM4 clock recovery (CDR) architecture. A three-lane quarter-rate detector with majority voter was employed to suppress input caused discrete zero-crossings, an optimized quadrature voltage-controlled oscillator (QVCO) designed provide stable precise The CDR optimally based on IHP 0.13µm SiGe BiCMOS process, post-simulation results indicates that our can operate properly at 100Gb/s peak-to-peak 5.52ps.